Verification Engineer
מעבר למשרות נוספות אלביט מערכות בע"מ
פורסם לפני 6 ימים
- חולון
- משרה מלאה
- לא צוין שכר
תיאור המשרה:
Elbit Systems Ltd. is an international technology company that specializes in defense, homeland security, and commercial programs worldwide
The company operates in aerospace, land, and naval systems, C4ISR, unmanned aircraft systems, advanced electro-optics, EW suites, signal intelligence systems, data links and communications systems, radios and cyber-based systems, and munitions
Elbit Systems develops new technologies for defense, homeland security, and commercial applications
Role Description:
We are seeking a Verification Engineer to join our dynamic team, specializing in System Verilog and UVM methodology
You will be responsible for designing and implementing verification plans, utilizing UVM to ensure comprehensive coverage and efficiency, Plan the verification of complex digital design by fully understanding the design specification and the implemented algorithms
You will collaborate with cross-functional teams to identify and resolve design issues, and contribute to the continuous improvement of our verification processes, Working closely with architecture, design and algorithm teams to identify important verification scenarios
Your contributions will have a direct impact on our vital defense capabilities
Key Responsibilities:
Responsible for the entire Verification cycle, from initial requirements gathering to achieving full coverage
Steps will include developing a detailed Test Plan, creating and optimizing the UVM environment, implementing comprehensive Coverage strategies, and integrating a Scoreboard for effective verification and validation
Collaborate closely with a multidisciplinary team of engineers to ensure our FPGA solutions align with the stringent requirements of our high-performance end products
Adapt to evolving project needs, demonstrating flexibility and innovation in your approach
The company operates in aerospace, land, and naval systems, C4ISR, unmanned aircraft systems, advanced electro-optics, EW suites, signal intelligence systems, data links and communications systems, radios and cyber-based systems, and munitions
Elbit Systems develops new technologies for defense, homeland security, and commercial applications
Role Description:
We are seeking a Verification Engineer to join our dynamic team, specializing in System Verilog and UVM methodology
You will be responsible for designing and implementing verification plans, utilizing UVM to ensure comprehensive coverage and efficiency, Plan the verification of complex digital design by fully understanding the design specification and the implemented algorithms
You will collaborate with cross-functional teams to identify and resolve design issues, and contribute to the continuous improvement of our verification processes, Working closely with architecture, design and algorithm teams to identify important verification scenarios
Your contributions will have a direct impact on our vital defense capabilities
Key Responsibilities:
Responsible for the entire Verification cycle, from initial requirements gathering to achieving full coverage
Steps will include developing a detailed Test Plan, creating and optimizing the UVM environment, implementing comprehensive Coverage strategies, and integrating a Scoreboard for effective verification and validation
Collaborate closely with a multidisciplinary team of engineers to ensure our FPGA solutions align with the stringent requirements of our high-performance end products
Adapt to evolving project needs, demonstrating flexibility and innovation in your approach
דרישות המשרה:
Skills and Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field
Four years of experience with UVM methodology and System Verilog
Experience with RTL debugging from Block level to System Level
Experience with Questa Simulator - advantage
VHDL/Verilog proficiency – advantage
TCL/Python/bash experience – advantage
Linux/NC experience – advantage
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field
Four years of experience with UVM methodology and System Verilog
Experience with RTL debugging from Block level to System Level
Experience with Questa Simulator - advantage
VHDL/Verilog proficiency – advantage
TCL/Python/bash experience – advantage
Linux/NC experience – advantage
מעבר למשרות דומות בתחומים:
משרה מספר 9245227
metapel
על החברה:
אלביט מערכות בע"מ
גודל חברה: 10001+
תעשייה: הגנה וחלל
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